MC68EC000 Motorola, MC68EC000 Datasheet - Page 18

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

1.2 DEVELOPMENT CYCLE
There are several steps that must be followed in order to create a FlexCore integrated mi-
croprocessor with an SCM68000. Figure 1-2 illustrates the standard cell design flow and the
tools required to complete each step. These steps include:
MOTOROLA
• Convert Design to Standard Cells Design—Begin by implementing the required system
• Capture Design on Workstation—Use the engineering workstation to capture the logic
• Logic Synthesis—The structural level description of the design is mapped to a more ef-
• Generate Test Patterns—The stimulus and test patterns for the design are generated
• Functional Simulation—Ensure that the logic of the schematic is functionally sound by
• Calculate Node Delays— Motorola software (mdaDecal) calculates the estimated prop-
• Path Delay Analysis—With path delay information from the Veritime software, the de-
• Perform Real-Time Simulation—The real-time simulation is run to verify full functionality
• Extract Test Vectors—The simulator records the input/output patterns generated during
• Automatic Place & Route—The circuit’s physical layout is created from the netlist using
• Interconnect Analysis—After the cells are placed and routed, the interconnect capaci-
• Re-Simulate—The circuit is re-simulated with Verilog to ensure no problems have aris-
functions with an SCM68000, peripherals, memory blocks, and cells from the Motorola
standard cell library.
schematic of cells and their interconnections.
ficient structural description, which is accomplished by converting the Boolean equa-
tions for the design to a two-level sum of products representation and minimized.
for the functional simulation.
using Verilog, the encrypted C models and synthesis models provided by Motorola. No
timing information is yet associated with the simulations, and all propagation delays are
preset to 1 ns.
agation delays of each node in the circuit. The design software estimates delays based
on the fanout, drive characteristics, and estimated interconnect capacitances of the
netlist and reveals potential timing problems.
lays between the clocked elements of the circuit can be determined, and the critical
paths that limit the clock rate can be identified. Checking for setup, hold, and pulse-
width violations can also be accomplished.
using the estimated propagation delays calculated by the design tools.
the real-time simulation. The test vectors that Motorola will use to test the prototypes
are derived from these patterns.
automatic place and route software.
tances are extracted. These capacitances replace those estimated earlier during the
calculation of the node delays.
en due to a change in load conditions. If changes have occurred or the simulation is dif-
ferent in any way, the test vectors must also be extracted again.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Overview
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