MC68EC000 Motorola, MC68EC000 Datasheet - Page 93

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
The bus cycle ends in S7 when the SCM68000 negates the address and data strobes, and
the test clock goes low. The AVECB signal must be removed within one clock cycle after the
negation of address strobe.
Data transfer acknowledge (DTACKB) must not be asserted while AVECB is asserted. The
state machine in the processor looks for DTACKB to identify an asynchronous bus cycle and
4-8
IPLB2–IPLB0
Figure 4-3. Autovector Operation Timing Diagram
NOTE:
SIZ1–SIZ0
FC2–FC0
DTACKB
D15–D8
A31–A4
AVECB
TSCAE
D7–D0
ERWB
A3–A1
RMCB
COEB
UDSB
DOEB
AOEB
LDSB
*
RWB
CLKI
ASB
DSB
Although both UDSB and LDSB are asserted, no data is read from the bus during the
autovector cycle. The vector number is generated internally.
An autovector operation will take between 10 and 18 clock cycles. See the best
and worst case examples on the following pages.
A0
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
S0 S2
STACK LOW
PC ON SSP
WORD OF
S4
Go to: www.freescale.com
S6
S0 S2 S4
S6 S6 S8
AUTOVECTOR *
OPERATION
S12
S16
S20
MOTOROLA