MC68EC000 Motorola, MC68EC000 Datasheet - Page 48

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

STATE 1
STATE 2
STATE 3
STATE 4
CASE 1: DTACKB is received alone or with BERRB (see 3.4 Bus Error and Halt Opera-
tion ).
STATE 5
STATE 6
STATE 7
CASE 2: BERRB is received without DTACKB (see 3.4 Bus Error and Halt Operation ).
STATE 5
STATE 6
STATE 7
STATE 8
MOTOROLA
Entering state 1 (S1), TSCAE is driven low to indicate the beginning of the bus cycle.
On the rising edge of state 2 (S2), the SCM68000 asserts ASB, UDSB, LDSB, and DSB.
During state 3 (S3), no bus signals are altered.
During state 4 (S4), the SCM68000 waits for a cycle termination signal (DTACKB or
BERRB) If neither termination signal is asserted before the falling edge at the end of S4,
the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is as-
serted. See 3.7 The Relationship of DTACKB, BERRB, and HALTIB for a description
of how DTACKB and BERRB interact.
During state 5 (S5), no bus signals are altered.
Sometime between state 2 (S2) and state 6 (S6), data from the device is driven onto the
data bus.
On the falling edge of the clock entering state 7 (S7), the SCM68000 latches data from
the addressed device and negates ASB, UDSB, LDSB, and DSB. The device negates
DTACKB or BERRB at this time.
During state 5 (S5), no bus signals are altered.
During state 6 (S6), no bus signals are altered.
During state 7 (S7), no bus signals are altered.
During state 8 (S8), no bus signals are altered.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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Bus Operation
3-7