MC68EC000 Motorola, MC68EC000 Datasheet - Page 107

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
Exception processing for privilege violations is similar to that of illegal instructions. After the
instruction is fetched and decoded and the SCM68000 determines that a privilege violation
is being attempted, the SCM68000 starts exception processing. The status register is cop-
ied; the supervisor mode is entered; and tracing is turned off. The vector number is gener-
ated to reference the privilege violation vector, and the current program counter and the
copy of the status register are saved on the supervisor stack. Finally, instruction execution
commences at the address in the privilege violation exception vector.
4.3.6 Tracing
To aid in program development, the M68000 Family includes a facility to allow tracing fol-
lowing each instruction. When tracing is enabled, an exception is forced after each instruc-
tion is executed. Thus, a debugging program can monitor the execution of the program
under test.
The trace function is controlled by the T-bit in the supervisor portion of the status register. If
the T-bit is cleared (off), tracing is disabled and instruction execution proceeds normally. If
the T-bit is set (on) at the beginning of the execution of an instruction, a trace exception is
generated after the instruction is completed. If the instruction is not executed because an
interrupt is taken or because the instruction is illegal or privileged, the trace exception does
not occur. The trace exception also does not occur if the instruction is aborted by the reset,
bus error, or address error exceptions. If the instruction is executed and an interrupt is pend-
ing upon completion, the trace exception is processed before the interrupt exception. During
the execution of the instruction, if an exception is forced by that instruction, the exception
processing for the instruction exception occurs before that of the trace exception.
As an extreme illustration of these rules, consider the arrival of an interrupt during the exe-
cution of a TRAP instruction while tracing is enabled. First, the trap exception is processed,
then the trace exception, and finally, the interrupt exception. Instruction execution resumes
in the interrupt handler routine.
After the execution of the instruction is complete and before the start of the next instruction,
exception processing for a trace begins. A copy is made of the status register. The transition
to supervisor mode is made, and the T-bit of the status register is turned off, disabling further
tracing. The vector number is generated to reference the trace exception vector, and the cur-
rent program counter and the copy of the status register are saved on the supervisor stack.
The saved value of the program counter is the address of the next instruction. Instruction
execution commences at the address contained in the trace exception vector.
4.3.7 Bus Error
A bus error exception is requested by external logic. The current bus cycle is terminated.
The current SCM68000 activity, whether instruction or exception processing, is terminated,
and the SCM68000 immediately begins exception processing.
Exception processing for a bus error follows the usual sequence of steps. The status register
is copied, the supervisor mode is entered, and tracing is turned off. The vector number is
generated to refer to the bus error vector. Since the SCM68000 is fetching the instruction or
an operand when the error occurs, the context of the SCM68000 is more detailed. To save
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EC000 CORE PROCESSOR USER’S MANUAL
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