MC68EC000 Motorola, MC68EC000 Datasheet - Page 92

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Although the timing diagram in Figure 4-2 is for the 16-bit mode, the following list describes
the sequence of events executed by the processor for a vectored and autovectored interrupt
in either mode.
4.1.5.2 AUTOVECTORED INTERRUPT ACKNOWLEDGE CYCLE. An interrupt acknowl-
edge cycle can be autovectored if AVECB is asserted instead of DTACKB in state 4 (S4).
For an autovectored interrupt, the vector number is internally generated to be $18 plus the
interrupt level. The autovector capability provides vectors for each of the six maskable inter-
rupt levels and for the nonmaskable interrupt level. The timing diagram for an autovectored
interrupt acknowledge cycle is shown in Figure 4-3.
After recognizing AVECB, the processor waits until the test clock (TESTCLK) signal is low.
Figure 4-4 shows the best-case timing of an autovectored interrupt acknowledge cycle,
while Figure 4-5 shows the worst-case timing. The cycle length is entirely dependent on the
relationship of the assertion of AVECB to the test clock.
When AVECB is recognized on the falling edge of S4 no extra wait states are inserted. The
only wait states inserted are those required to synchronize AVECB with the test clock. The
synchronization delay is an integral number of system clock cycles within the following ex-
tremes:
MOTOROLA
1. Make an internal copy of the current status register.
2. In the status register, set the S bit, clear the T bit, and replace the interrupt mask with
3. Stack the lower word of the program counter on the supervisor stack.
4. Run an interrupt acknowledge bus cycle for vector number acquisition. This step takes
5. Justify the vector number for vector acquisition. No bus activity occurs during the four
6. Stack the status register that was saved in step 1 on the supervisor stack.
7. Stack the upper word of the program counter on the supervisor stack.
8. Read the upper word of the exception vector.
9. Read the lower word of the exception vector.
10. Fetch the first word of the first instruction of the interrupt handler routine.
11. Continue fetching instructions and executing as normal until the interrupt handling rou-
1. Best Case—the assertion of AVECB is recognized on the falling edge of the system
2. Worst Case—the assertion of AVECB is recognized on the falling edge of the system
the level of the interrupt that was recognized. No bus activity occurs during the six
clocks required to complete steps 1 and 2.
four clock cycles with no wait states. For an autovectored interrupt, this step takes ten
to eighteen clock cycles.
clock periods that are required for this step.
tine is complete.
clock that occurs three clock cycles before TESTCLK rises (or three clock cycles after
TESTCLK falls).
clock that occurs two clock cycles before TESTCLK rises (or four clock cycles after
TESTCLK falls).
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
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Exception Processing
4-7