MC68EC000 Motorola, MC68EC000 Datasheet - Page 115

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

8-Bit Instruction Execution Times
5.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES
Table 5-8 lists the timing data for the shift and rotate instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
5.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMESS
Table 5-9 lists the timing data for the bit manipulation instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
5.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 5-10 lists the timing data for the conditional instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the previ-
ously described format. The number of clock periods, the number of read cycles, and the
number of write cycles, respectively, must be added to those of the effective address calcu-
lation where indicated by a plus sign (+).
5-6
BCHG
BCLR
BSET
BTST
+ Add effective address calculation time.
* Indicates maximum value; data addressing mode only.
Instruction
Table 5-9. Bit Manipulation Instruction Execution Times
Table 5-8. Shift/Rotate Instruction Execution Times
ASR, ASL
LSR, LSL
ROR, ROL
ROXR, ROXL
+ Add effective address calculation time for word operands.
n is the shift count.
Instruction
Long
Long
Long
Long
Size
Byte
Byte
Byte
Byte
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EC000 CORE PROCESSOR USER’S MANUAL
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Word
Word
Word
Word
Register
Long
Long
Long
Long
Size
Byte
Byte
Byte
Byte
12(2/0)*
14(2/0)*
12(2/0)*
10(2/0)
—
—
—
—
Dynamic
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
10+2n(2/0)
10+2n(2/0)
12+n2(2/0)
Register
Memory
12(2/1)+
12(2/1)+
12(2/1)+
8(2/0)+
—
—
—
Register
20(4/0)*
22(4/0)*
20(4/0)*
18(4/0)
Memory
16(2/2)+
16(2/2)+
16(2/2)+
16(2/2)+
—
—
—
—
—
—
—
—
—
—
—
—
Static
Memory
20(4/1)+
20(4/1)+
20(4/1)+
16(4/0)+
—
—
—
—
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