MC68EC000 Motorola, MC68EC000 Datasheet - Page 59

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Bus Operation
3.2.1 Requesting the Bus
External devices capable of becoming bus masters assert BRB to request the bus. This sig-
nal can be ORed (not necessarily constructed from open-collector devices) from any of the
devices in the system that can become bus master. The SCM68000, which is at a lower bus
priority level than the external devices, relinquishes the bus after it completes the current
bus cycle.
When no acknowledge is received before the bus request signal is negated, the SCM68000
continues to use the bus. Also, BGACKB allows arbitration time for another bus master to
be overlapped with bus cycles to lessen bus idle time.
3.2.2 Receiving the Bus Grant
After BRB is asserted, the SCM68000 asserts BGB immediately following internal synchro-
nization. The exception to this is when the SCM68000 has made an internal decision to exe-
cute the next bus cycle but has not yet asserted ASB for that cycle. In this case, BGB is
delayed until ASB is asserted to indicate to external devices that a bus cycle is in progress.
3-18
1) NEGATE BGB (AND WAIT FOR BGACKB
1) ASSERT BUS GRANT (BGB)
TO BE NEGATED)
TERMINATE ARBITRATION
REARBITRATE OR RESUME
GRANT BUS ARBITRATION
PROCESSOR OPERATION
PROCESSOR
Figure 3-14. 3-Wire Bus Arbitration Cycle Flowchart
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
1) PERFORM DATA TRANSFERS (READ
1) EXTERNAL ARBITRATION DETER-
2) NEXT BUS MASTER WAITS FOR
3) NEXT BUS MASTER ASSERTS BUS
4) BUS MASTER NEGATES BRB
1) ASSERT BUS REQUEST (BRB)
1) NEGATE BGACKB
ACKNOWLEDGE BUS MASTERSHIP
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO-
CESSOR USES
MINES NEXT BUS MASTER
CURRENT CYCLE TO COMPLETE
GRANT ACKNOWLEDGE (BGACKB)
TO BECOME NEW MASTER
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
REQUESTING DEVICE
REQUEST THE BUS
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