MC68EC000 Motorola, MC68EC000 Datasheet - Page 108

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

more of this context, additional information is saved on the supervisor stack. The program
counter and the copy of the status register are saved. The value saved for the program
counter is advanced 2–10 bytes beyond the address of the first word of the instruction that
made the reference causing the bus error. If the bus error occurred during the fetch of the
next instruction, the saved program counter has a value in the vicinity of the current instruc-
tion, even if the current instruction is a branch, a jump, or a return instruction. In addition to
the usual information, the SCM68000 saves its internal copy of the first word of the instruc-
tion being processed and the address being accessed by the aborted bus cycle. Specific
information about the access is also saved: type of access (read or write), SCM68000 activ-
ity (processing an instruction), and function code outputs when the bus error occurred. The
SCM68000 is processing an instruction if it is in the normal state or processing a group 2
exception; the SCM68000 is not processing an instruction if it is processing a group 0 or a
group 1 exception (see Table 4-3 for more information on exception groups). Figure 4-14
illustrates how this information is organized on the supervisor stack. If a bus error occurs
during the last step of exception processing, while either reading the exception vector or
fetching the instruction, the value of the program counter is the address of the exception vec-
tor. Although this information is not generally sufficient to fully recover from the bus error, it
does allow software diagnosis. Finally, the SCM68000 commences instruction processing
at the address in the vector. It is the responsibility of the error handler routine to clean up
the stack and determine where to continue execution.
If a bus error or address error occurs during the exception processing for a bus error, an
address error, or a reset, the SCM68000 halts and all processing ceases. This halt simplifies
the detection of a catastrophic system failure, since the SCM68000 removes itself from the
system to protect memory contents from erroneous accesses. Only an external reset oper-
ation can restart a halted SCM68000.
4.3.8 Address Error
An address error exception occurs when the SCM68000 attempts to access a word or long-
word operand or an instruction at an odd address. An address error is similar to an internally
generated bus error. The bus cycle is aborted, and the SCM68000 ceases current process-
MOTOROLA
LOWER ADDRESS
Figure 4-14. Supervisor Stack Order for Bus or Address Error Exception
R/W (Read/Write): Write = 0, Read = 1. I/N (Instruction/Not): Instruction = 0, Not = 1
15
ACCESS ADDRESS
PROGRAM COUNTER
14
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
13
12
Go to: www.freescale.com
11
10
9
INSTRUCTION REGISTER
STATUS REGISTER
8
HIGH
LOW
HIGH
LOW
7
6
5
R/W
4
Exception Processing
I/N
3
2
FUNCTION CODE
1
0
4-23