MC68EC000 Motorola, MC68EC000 Datasheet - Page 30

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

SECTION 2
SIGNAL DESCRIPTION
This section contains descriptions of the SCM68000 (EC000 core)
The input and output signals are shown in Figure 2-1. Table 2-1 lists the pins, signal names,
type, and whether they are three-stateable. The following paragraphs provide brief descrip-
tions of the signals and references (where applicable) to other paragraphs that contain more
information about the signals.
2.1 ADDRESS BUS (A31–A0)
This 32-bit, unidirectional, three-state bus is capable of addressing 4 Gbytes of address
space. This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3
provide the level number of the interrupt being acknowledged, and address lines A31–A4
and A0 are driven to a logic high.
2.2 DATA BUS (D15–D0)
This 16-bit, bidirectional, three-state bus is the general-purpose data-path. The data bus
transfers and accepts data in either word or byte length if the SCM68000 is operating in the
16-bit mode. If the SCM68000 is operating in the 8-bit mode, it drives the entire bus during
writes, but only the lower eight bits (D7–D0) contain valid data. In the 8-bit mode, the
SCM68000 ignores the data on data lines D15–D8 during read cycles. During an interrupt
acknowledge cycle, the external device supplies the vector number on data lines D7–D0.
2.3 CLOCK (CLKI, CLKO)
The CLKI input is internally buffered for development of the internal clocks needed by the
SCM68000. This clock signal is a constant-frequency square wave that requires no stretch-
ing or shaping. The clock signal must conform to minimum and maximum pulse-width times
1.
MOTOROLA
The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section will
refer to the EC000 core as only the SCM68000.
The terms assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of "active-
low" and "active-high" signals. The term assert or assertion is
used to indicate that a signal is active or true, independently of
whether that level is represented by a high or low voltage. The
term negate or negation is used to indicate that a signal is inac-
tive or false.
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
NOTE
1
input and output signals.
2-1