MC68EC000 Motorola, MC68EC000 Datasheet - Page 26

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Overview
1-13
<operand> rotated by
<operand> shifted by
bit number of <oper-
<operand> sign-ex-
#<xxx> or #<data>
tended <operand>
then <operations>
<operand> tested
else <operations>
<operand> 10
If <condition>
<operand>
<count>
<count>
Ax, Ay
Dx, Dy
Rx, Ry
TRAP
STOP
<fmt>
and>
CCR
PC
SR
An
Dn
Rn
Xn
d n
( )
[ ]
+
–
~
V
<
>
Not equal.
Arithmetic addition or postincrement indicator.
Arithmetic subtraction or predecrement indicator.
Arithmetic multiplication.
Arithmetic division or conjunction symbol.
Invert; operand is logically complemented.
Logical AND
Logical OR
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
Relational test; true if source operand is less than destination operand.
Relational test; true if source operand is greater than destination operand.
Data used as an operand.
Operand is compared to zero and the condition codes are set appropriately.
All bits of the upper portion are made equal to the high-order bit of the lower portion.
The source operand is shifted by the number of count.
The source operand is rotated by the number of count.
Selects a single bit of the operand.
1
SSP – 4
SR
Enter the stopped state, waiting for interrupts.
The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then” are performed. If the condition is false and
the optional “else” clause is present, the operations after “else” are performed. If the condition
is false and "else" is omitted, the instruction performs no operation. Refer to the Bcc instruction
description as an example.
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively.
Any Data Register n (example: D5 is data register 5)
Source and destination data registers, respectively.
Any Address or Data Register
Any source and destination registers, respectively.
Index Register—An, Dn, or suppressed.
Operand Data Format: Byte (B), Word (W), Long (L)
Immediate data following the instruction word(s).
Identifies an indirect address in a register.
Identifies an indirect address in memory.
Displacement Value, n Bits Wide (example: d 16 is a 16-bit displacement).
Condition Code Register (lower byte of status register)
Program Counter
Status Register
S-bit of SR;
(SSP); Vector Address
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
Table 1-2. Notational Conventions
For More Information On This Product,
SSP; PC
Single- and Double-Operand Operations
Go to: www.freescale.com
Subfields and Qualifiers
Register Specification
Data Format and Type
(SSP); SSP – 2
Other Operations
Register Names
PC
SSP;
MOTOROLA