MC68EC000 Motorola, MC68EC000 Datasheet - Page 99

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

Exception Processing
processing finally commences in the interrupt handler routine. A summary of exception
grouping and priority is given in Table 4-3.
As an example, consider trap, trace, and interrupt exceptions that occurred simultaneously
and are pending. The exception processing for the trap occurs first, followed immediately by
exception processing for the trace, and then for the interrupt. When the SCM68000 resumes
normal instruction execution, it is in the interrupt handler, which returns to the trace handler,
which returns to the trap execution handler. The reset exception handler is always executed
first because it clears all other exceptions.
4.2.4 Exception Stack Frames
Exception processing saves the most volatile portion of the current SCM68000 context on
the top of the supervisor stack. This context is organized in a format called the exception
stack frame. Although this information varies with type of exception, it always includes the
status register and program counter of the SCM68000 when the exception occurred.
The amount and type of information saved on the stack are determined by the exception
type. Exceptions are grouped by type according to priority of the exception.
Of the group 0 exceptions, the reset exception does not stack any information. The informa-
tion stacked by a bus error or address error exception is described in 4.3.7 Bus Error and
is shown in Figure 4-14.
The groups 1 and 2 exception stack frame is shown in Figure 4-9. Only the program counter
and status register are saved. The program counter points to the next instruction to be exe-
cuted after exception processing.
4.2.5 Exception Processing Sequence
In the first step of exception processing, an internal copy is made of the status register. After
the copy is made, the S-bit of the status register is set, putting the SCM68000 into the super-
visor mode. Also, the T-bit is cleared, which allows the exception handler to execute unhin-
dered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also
updated appropriately.
In the second step, the vector number of the exception is determined. For interrupts, the vec-
tor number is obtained by an SCM68000 bus cycle classified as an interrupt acknowledge
4-14
Group
0
1
2
TRAP, TRAPV
Divide-by-Zero
Address Error
Exception
Bus Error
Privilege
Interrupt
Reset
Trace
Illegal
CHK
Table 4-3. Exception Grouping and Priority
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Exception Processing Begins as Soon as the Bus Cycle Is Terminated
Exception Processing Begins Before the Next Instruction
Exception Processing Is Started by Normal Instruction Execution
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Processing
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