MC68EC000 Motorola, MC68EC000 Datasheet - Page 54

• Manufacturer Part Number: MC68EC000
• Description: Core Processor (SCM 68000)
• Manufacturer: Motorola

STATE 9
3.1.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe (ASB) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between pro-
cessors in a multiprocessing environment. The TAS instruction (the only instruction that
uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write cycles
are byte operations. The read-modify-write flowchart is shown in Figure 3-12 and the timing
diagram is shown in Figure 3-13.
MOTOROLA
During state 9 (S9), ASB, UDSB, LDSB, and DSB are negated. The device negates
BERRB at this time. At the end of S9, the data bus is placed in the high-impedance state,
and RWB and ERWB are driven to a logic high.
1) SET RWB AND ERWB TO WRITE
2) PLACE DATA ON D7–D0 OR D15–D8
3) ASSERT UPPER DATA STROBE (UDSB)
1) SET RWB AND ERWB TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A31–A0
4) ASSERT ADDRESS STROBE (ASB)
5) ASSERT UPPER DATA STROBE (UDSB)
6) ASSERT RMCB
1) LATCH DATA
1) NEGATE UDSB AND LDSB
2) START DATA MODIFICATION
1) NEGATE UDSB AND LDSB
2) NEGATE ASB
3) REMOVE DATA FROM D7–D0 OR
4) SET RWB AND ERWB TO READ
5) NEGATE RMCB
OR LOWER DATA STROBE (LDSB)
AND DATA STROBE (DSB)
OR LOWER DATA STROBE (LDSB)
AND DATA STROBE (DSB)
D15–D8
TERMINATE OUTPUT TRANSFER
START OUTPUT TRANSFER
ADDRESS THE DEVICE
ACQUIRE THE DATA
START NEXT CYCLE
BUS MASTER
Figure 3-12. Read-Modify-Write Cycle Flowchart
Freescale Semiconductor, Inc.
EC000 CORE PROCESSOR USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
1) REMOVE DATA FROM D7–D0
2) NEGATE DTACKB
1) DECODE ADDRESS
2) PLACE DATA ON D7–D0 OR D15–D8
3) ASSERT DATA TRANSFER
1) STORE DATA ON D7–D0 OR D15–D8
2) ASSERT DATA TRANSFER
1) NEGATE DTACKB
OR D15–D8
ACKNOWLEDGE (DTACKB)
ACKNOWLEDGE (DTACKB)
TERMINATE THE CYCLE
TERMINATE THE CYCLE
OUTPUT THE DATA
INPUT THE DATA
SLAVE
Bus Operation
3-13