R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 340

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 307 of 723
Figure 20.3
20.2.2
Table 20.4
i = 0 or 1
Input capture function
Output compare function
PWM mode
Reset synchronous PWM
mode
Complementary PWM
mode
PWM3 mode
Function and Mode
The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the
TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi
in the TRDMR register.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
Buffer operation depends on the mode. Table 20.4 lists the Buffer Operation in Each Mode.
i = 0 or 1
The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
Buffer Operation
the TRDGRAi register).
Buffer Operation in Each Mode
Buffer Operation in Input Capture Function
TRDGRCi register
TRDGRAi register
TRDIOAi input
TRDi register
TRDIOAi input
(input capture signal)
TRDGRCi register
(buffer)
Input capture signal input
Compare match with TRDi register
and TRDGRAi (TRDGRBi) register
Compare match withTRD0 register
and TRDGRA0 register
• Compare match with TRD0 register
• TRD1 register underflow
Compare match with TRD0 register
and TRDGRA0 register
(buffer)
and TRDGRA0 register
Transfer Timing
n-1
m
TRDGRAi
register
n
Transfer
Transfer
Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
registers TRDGRB0, TRDGRA1, and
TRDGRB1
Transfer content in buffer register to
registers TRDGRA0, TRDGRB0,
TRDGRA1, and TRDGRB1
m
n
Transfer Register
n+1
TRDi
20. Timer RD