R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 557
R5F21346CNFP#U0
Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet
1.R5F21346CNFPU0.pdf
(759 pages)
Specifications of R5F21346CNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 524 of 723
25.5
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and
a chip select line is used for communication. This mode includes bidirectional mode in which the data input line
and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the
BIDE bit in the SSMR2 register. For details, refer to 25.3.2.1 Association between Data I/O Pins and SS Shift
Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in the
SSMR register. For details, refer to 25.3.1.1 Association between Transfer Clock Polarity, Phase, and Data.
When this MCU is set as the master device, the chip select line controls output. When synchronous serial
communication unit is set as a slave device, the chip select line controls input. When it is set as the master device,
the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the
CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as an
input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed
MSB-first.
Operation in 4-Wire Bus Communication Mode
25. Synchronous Serial Communication Unit (SSU)
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