R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 548

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 515 of 723
25.3.3
Table 25.3
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
If the generation conditions in Table 25.3 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 by a synchronous serial communication unit interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
Synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive
data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial
communication unit interrupt vector table, determining interrupt sources by flags is required.
Table 25.3 shows the Synchronous Serial Communication Unit Interrupt Requests.
Interrupt Request
Interrupt Requests
Synchronous Serial Communication Unit Interrupt Requests
TXI
TEI
RXI
OEI
CEI
Abbreviation
25. Synchronous Serial Communication Unit (SSU)
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
Generation Condition

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