R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 609

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 576 of 723
Figure 27.5
27.4.2
LINCR register
TRAIC register
LINST register
LINST register
RXDSF flag in
SBDCT flag in
SFDCT flag in
Figure 27.5 shows an Operating Example during Header Field Reception in slave mode. Figure 27.6 through
Figure 27.8 show examples of Header Field Reception Flowchart.
During header field reception, the hardware LIN operates as follows:
(1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is
(2) If a “L” level is input for a duration equal to or longer than the period set in timer RA, the hardware LIN
(3) The hardware LINA receives a Synch Field (55h) and measures the period of the start bit and bits 0 to 6 is
(4) When the Synch Field measurement is completed, the SFDCT flag in the LINST register is set to 1. If the
(5) After the Synch Field measurement is completed, a transfer rate is calculated from the timer RA count
(6) After the hardware LIN completes receiving the ID field, it performs communication for a response field.
RXD0 input
for UART0
RXD0 pin
enabled.
detected it as a Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. If the SBIE bit
in the LINCR register is set to 1, a timer RA interrupt is generated. Then the hardware LIN enters the Synch
Field measurement.
using timer RA. At this time, whether to input the Synch Field signal to RXD0 of UART0 can be selected
by the SBE bit in the LINCR register.
SFIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
value. The rate is set in UART0 and registers TRAPRE and TRA for timer RA are set again. Then the
hardware LIN receives an ID field via UART0.
IR bit in
Slave Mode
Operating Example during Header Field Reception
The above applies when:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
(1)
1 is written to LSTART bit
in LINCR register.
Synch Break
(2)
(3)
This period is measured.
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B1CLR bit
in LINST register.
Synch Field
(4)
(5)
1 is written to B0CLR bit
in LINST register.
The flag is set to 0 after Synch Field
measurement is completed.
IDENTIFIER
(6)
27. Hardware LIN