R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 403
R5F21346CNFP#U0
Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet
1.R5F21346CNFPU0.pdf
(759 pages)
Specifications of R5F21346CNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 370 of 723
20.6.10 Timer RD Status Register i (TRDSRi) (i = 0 or 1) in Reset Synchronous
Notes:
After Reset
After Reset
1. Nothing is assigned to b5 in the TRDSR0 register. When writing to b5, write 0. When reading, the content is 1.
2. The writing results are as follows:
3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0143h (TRDSR0), 0153h (TRDSR1)
• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even
• This bit remains unchanged if 1 is written to it.
Symbol
if it is set to 1 from 0 after reading, and writing 0.)
Symbol
Bit
IMFC
IMFD
IMFA
IMFB
OVF
UDF
PWM Mode
—
—
b7
—
1
1
Input capture / compare match flag A [Source for setting this bit to 0]
Input capture / compare match flag B [Source for setting this bit to 0]
Input capture / compare match flag C [Source for setting this bit to 0]
Input capture / compare match flag D [Source for setting this bit to 0]
Overflow flag
Underflow flag
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b6
—
1
1
Bit Name
(1)
UDF
b5
1
0
OVF
b4
0
0
Write 0 after read
[Source for setting this bit to 1]
When the value in the TRDi register matches with
the value in the TRDGRAi register.
Write 0 after read
[Source for setting this bit to 1]
When the value in the TRDi register matches with
the value in the TRDGRBi register.
Write 0 after read
[Source for setting this bit to 1]
When the value in the TRDi register matches with
the value in the TRDGRCi register
Write 0 after read
[Source for setting this bit to 1]
When the value in the TRDi register matches with
the value in the TRDGRDi register
[Source for setting this bit to 0]
Write 0 after read
[Source for setting this bit to 1]
When the TRDi register overflows.
This bit is disabled in reset synchronous PWM
mode.
IMFD
b3
0
0
IMFC
b2
0
0
(2)
(2)
(2)
(2)
(2)
.
.
.
.
.
Function
IMFB
b1
0
0
IMFA
b0
0
0
(3)
(3)
.
.
TRDSR0 register
TRDSR1 register
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
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