R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 369

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 336 of 723
20.4.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Output Compare
Notes:
After Reset
1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the
2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.
3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to
4. This setting is enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0140h (TRDCR0), 0150h (TRDCR1)
TRDFCR register is 1 (external clock input enabled).
0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
synchronously).
Symbol
Symbol
CKEG0 External clock edge select bit
CKEG1
CCLR0 TRDi counter clear select bit
CCLR1
CCLR2
Bit
TCK0
TCK1
TCK2
Function
CCLR2
b7
0
Count source select bit
CCLR1
b6
0
Bit Name
CCLR0
b5
0
CKEG1
(3)
b4
0
b2 b1 b0
b4 b3
b7 b6 b5
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRDCLK input
1 1 0: fOCO40M
1 1 1: fOCO-F
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both edges
1 1: Do not set.
0 0 0: Disable clear (free-running operation)
0 0 1: Clear by compare match with the TRDGRAi
0 1 0: Clear by compare match with the TRDGRBi
0 1 1: Synchronous clear (clear simultaneously with
1 0 0: Do not set.
1 0 1: Clear by compare match with the TRDGRCi
1 1 0: Clear by compare match with the TRDGRDi
1 1 1: Do not set.
CKEG0
b3
0
register
register
other timer RDi counter)
register
register
TCK2
(5)
b2
0
(1)
Function
or fC2
TCK1
b1
0
(2)
(4)
TCK0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W