R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 389

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 356 of 723
20.5.13 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM Mode
20.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0144h (TRDIER0), 0154h (TRDIER1)
Address 0145h (TRDPOCR0), 0155h (TRDPOCR1)
Symbol
Symbol
Symbol
Symbol
Bit
IMIEA
IMIEB
IMIEC
IMIED
Bit
POLB
POLC
POLD
OVIE
1) in PWM Mode
—
—
—
—
—
—
—
—
b7
b7
—
—
1
1
Input capture/compare match interrupt
enable bit A
Input capture/compare match interrupt
enable bit B
Input capture/compare match interrupt
enable bit C
Input capture/compare match interrupt
enable bit D
Overflow/underflow interrupt enable
bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
PWM mode output level control bit B
PWM mode output level control bit C
PWM mode output level control bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
b6
b6
—
—
1
1
Bit Name
Bit Name
b5
—
b5
—
1
1
OVIE
b4
b4
—
0
1
0: Disable interrupt (IMIA) by the IMFA bit
1: Enable interrupt (IMIA) by the IMFA bit
0: Disable interrupt (IMIB) by the IMFB bit
1: Enable interrupt (IMIB) by the IMFB bit
0: Disable interrupt (IMIC) by the IMFC bit
1: Enable interrupt (IMIC) by the IMFC bit
0: Disable interrupt (IMID) by the IMFD bit
1: Enable interrupt (IMID) by the IMFD bit
0: Disable interrupt (OVI) by the OVF bit
1: Enable interrupt (OVI) by the OVF bit
0: “L” active TRDIOBi output level is selected
1: “H” active TRDIOBi output level is selected
0: “L” active TRDIOCi output level is selected
1: “H” active TRDIOCi output level is selected
0: “L” active TRDIODi output level is selected
1: “H” active TRDIODi output level is selected
IMIED
b3
b3
—
0
1
IMIEC
POLD
b2
b2
0
0
Function
Function
IMIEB
POLC
b1
b1
0
0
IMIEA
POLB
b0
b0
0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—