R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 359

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 326 of 723
Figure 20.9
TRDIOji input signal
20.3.18 Digital Filter
fOCO40M
TRDCLK
Sampling clock
TRDIOji input signal
Input signal through
digital filtering
fOCO-F
The TRDIOji (i = 0 or 1, j = A, B, C, or D) input is sampled, and when the sampled input level matches 3 times,
its level is determined. Select the digital filter function and sampling clock by the TRDDFi register.
Figure 20.9 shows a Block Diagram of Digital Filter.
fC2
f32
f8
f4
f2
f1
ITCLKi = 1
ITCLKi = 0
Timer RD operation clock
= 011b
i = 0 or 1, j = A, B, C, or D
ITCLK0, ITCLK1: Bits in TRDECR register
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
= 100b
Block Diagram of Digital Filter
= 010b
Clock period selected by
bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
= 101b
D
D
= 001b
f1, fOCO40M)
TCK2 to TCK0
= 000b
= 110b
Latch
Latch
C
C
= 111b
Q
Q
Count source
D
f32
f8
f1
Latch
C
= 01b
= 10b
= 00b
= 11b
DFCK1 to DFCK0
Q
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
detection
Match
circuit
Signal transmission delayed
up to 5-sampling clock
signal change with
Recognition of the
3-time match
1
0
DFj
Edge detection
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
circuit
20. Timer RD