R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 446

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 413 of 723
Figure 20.26
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
TRDSR0 register
TRDSR0 register
•
Count value in TRD0
The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0
in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in
the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is
transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation,
data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains
unchanged.
UDF bit in
OVF bit in
FFFFh
Operation when TRD1 Register Underflows in Complementary PWM Mode
register
1
0
0
Set to 0 by a program
Transferred from
buffer register
No change
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 10b
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
20. Timer RD