R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 61

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 28 of 723
Table 5.2 lists the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset,
Figure 5.3 shows the Reset Sequence.
Figure 5.2
Figure 5.3
Table 5.2
Internal reset
signal
P0 to P2, P6
P3_0 and P3_1, P3_3 to P3_5, P3_7 Input port
P4_2 to P4_7
CPU clock
Address
(internal address
signal)
RESET pin
fOCO-S
Notes:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same time.
Pin Name
CPU Register Status after Reset
Reset Sequence
Pin Functions while RESET Pin Level is “L”
10 µs or more are needed
b15
fOCO-S clock × 32 cycles
IPL
b19
Content of addresses 0FFFEh to 0FFFCh
Start time of flash memory
(CPU clock × 148 cycles)
b15
b15
b15
(1)
b8
(2)
00000h
Input port
Input port
U
b7
I
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
O
CPU clock × 28 cycles
B
S
Pin Function
Z
D
C
b0
b0
b0
b0
b0
0FFFCh
Interrupt table register (INTB)
Program counter (PC)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data register (R0)
Data register (R1)
Data register (R2)
Data register (R3)
Address register (A0)
Address register (A1)
Frame base register (FB)
0FFFDh
0FFFEh
Content of reset vector
5. Resets