S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 102

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 10
S1D13705
X27A-G-002-02
for (int loop = 0; loop < 2; loop++)
{
}
// If we still can't hit the frame rate - throw an error.
if ((VNDP < 0) || (VNDP > 0x3F) || (HNDP < 32) || (HNDP > 280))
{
}
for (VNDP = 2; VNDP < 0x3F; VNDP += 3)
{
}
// Divide ClkI and try again.
// (Reg[02] allows us to dived CLKI by 2)
PCLK /= 2;
sprintf("ERROR: Unable to set the desired frame rate.\n");
exit(1);
The following are the formulae for determining the frame rate of a panel. The formula for
a single passive or TFT panel is calculated as follows:
for a dual passive panel the formula is:
where: PCLK
In addition to varying the HNDP and VNDP times we can also select divider values which
will reduce CLKi to one half, one quarter up to one eight of the CLKi value. The example
below is a portion of a ’C’ routine to calculate HNDP and VNDP from a desired frame rate.
// Solve for HNDP
if ((HNDP >= 32) && (HNDP <= 280))
{
}
HNDP = (PCLK / (FrameRate * (VDP + VNDP))) - HDP;
HDP
HNDP
VDP
VNDP
FrameRate
// Solve for VNDP.
VNDP = (PCLK / (FrameRate * (HDP + HNDP))) - VDP;
// If we have satisfied VNDP then we're done.
if ((VNDP >= 0) && (VNDP <= 0x3F))
FrameRate
= Pixel clock (in Hz)
= Horizontal Display Period (in pixels)
= Horizontal Non-Display Period (in pixels)
= Vertical Display Period (in lines)
= Vertical Non-Display Period (in lines)
goto DoneCalc;
=
=
-------------------------------------------------------------------------------------------------- -
2
---------------------------------------------------------------------------------------- -
HDP
HDP
+
+
HNDP
HNDP
PCLK
PCLK
VDP
VDP
----------- -
2
+
VNDP
+
VNDP
Epson Research and Development
Programming Notes and Examples
Vancouver Design Center
Issue Date: 01/02/13