S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 401

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
4 MPC821 to S1D13705 Interface
4.1 Hardware Description
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/13
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MPC821 to S1D13705 Interface
The interface between the S1D13705 and the MPC821 requires minimal glue logic. One
inverter is required to change the polarity of the WAIT# signal (an active low signal) to
insert wait states in the bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an
active low signal which ends the current bus cycle. The inverter is enabled using CS# so
that TA is not driven by the S1D13705 during non-S1D13705 bus cycles. A single resistor
is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
The following diagram shows a typical implementation of the MPC821 to S1D13705
interface.
MPC821
A[15:31]
SYSCLK
D[0:15]
TA
WE0
WE1
CS4
OE
Vcc
470
System RESET
BUSCLK
RESET#
RD/WR#
AB[16:0]
DB[15:0]
BS#
CS#
RD#
WAIT#
WE1#
WE0#
S1D13705
X27A-G-010-02
S1D13705
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