S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 189

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
13705CFG Configuration Program
Issue Date: 01/03/29
The S1D13705 uses one clock input known as CLKI. The pixel clock (PCLK) and the
memory clock (MCLK) are both derived directly from CLKI.
CLKI
PCLK
MCLK
Source
Divide
Timing
Source
Divide
Timing
This setting determines the frequency of CLKI. CLKI is
the source for both PCLK and MCLK.
The CLKI frequency must be selected from the drop
down list or by entering the desired frequency in MHz.
The actual CLKI frequency used for configuration is
displayed in blue in the Actual section.
These settings confirm the signal source and input clock
divisor for the pixel clock (PCLK).
The PCLK source is CLKI.
The divide ratio for the clock source signal is 1:1.
This field shows the actual PCLK used by the configu-
ration process.
These settings confirm the signal source and input clock
divisor for the memory clock (MCLK).
The MCLK source is CLKI.
The divide ratio for the clock source signal is 1:1.
This field shows the actual MCLK frequency used by
the configuration process.
X27A-B-001-02
S1D13705
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