S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 304

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 10
3.2 Generic #1 Interface Mode
S1D13705
X27A-G-004-02
Generic #1 interface mode is the most general and least processor-specific interface mode
on the S1D13705. The Generic # 1 interface mode was chosen for this interface due to the
simplicity of its timing.
The interface requires the following signals:
• BUSCLK is a clock input which is required by the S1D13705 host interface. It is sepa-
• The address inputs AB0 through AB16, and the data bus DB0 through DB15, connect
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
• WAIT# is a signal output from the S1D13705 that indicates the host CPU must wait
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
rate from the input clock (CLKI) and is typically driven by the host CPU system clock.
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
register and memory address space.
to be driven low when the host CPU is writing data to the S1D13705. These signals
must be generated by external hardware based on the control outputs from the host CPU.
to be driven low when the host CPU is reading data from the S1D13705. These signals
must be generated by external hardware based on the control outputs from the host CPU.
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the S1D13705 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13705 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
However, BS# is used to configure the S1D13705 for Generic #1 mode and should be
tied low (connected to GND).
Interfacing to the Toshiba MIPS TMPR3912 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/13