S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 444

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 16
S1D13705
X27A-G-012-02
PR31500/PR31700
IT8368E
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
LHA[16:13]/
MFIO[3:0]
/CARDxWAIT
DCLKOUT
HD[31:24]
HD[23:16]
HA[12:0]
ENDIAN
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 5-1: S1D13705 to PR31500/PR31700 Connection Using an IT8368E
Note
The “Generic #1” host interface control signals of the S1D13705 are asynchronous with
respect to the S1D13705 bus clock. This gives the system designer full flexibility to choose
the appropriate source (or sources) for CLKI and BCLK. The choice of whether both clocks
should be the same, and whether to use DCLKOUT (divided) as clock source, should be
based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
See Section 3.1 on page 9 and Section 3.2 on page 10 for Generic #1 pin descriptions.
V
DD
Clock divider
pull-up
Interfacing to the Philips MIPS PR31500/PR31700 Processor
...or...
Oscillator
System RESET
Epson Research and Development
+3.3V
See text
Vancouver Design Center
RESET#
AB[12:0]
AB[16:13]
DB[7:0]
DB[15:8]
WAIT#
BS#
WE1#
WE0#
RD/WR#
RD#
CS#
IO V
CLKI
BCLK
Issue Date: 01/02/13
S1D13705
DD
, CORE V
DD