S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 475

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
4.2 S1D13705 Hardware Configuration
Interfacing to the NEC VR4181A™ Microprocessor
Issue Date: 01/02/13
CNF2
CNF0
CNF1
CNF2
CNF3
1
Signal
The host interface control signals of the S1D13705 are asynchronous with respect to the
S1D13705 bus clock. This gives the system designer full flexibility to choose the appro-
priate source (or sources) for CLKI and BCLK. The choice of whether both clocks should
be the same, and whether an external or internal clock divider is needed, should be based
on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
The S1D13705 uses CNF3 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the S1D13705 Hardware
Functional Specification, document number X27A-A-001-xx for details.
The tables below show those configuration settings important to the Generic #2 host bus
interface.
= configuration for NEC VR4181A support
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
= configuration for NEC VR4181A support
value on this pin at the rising edge of RESET# is used to configure: (0/1)
CNF1
1
Table 4-1: Summary of Power-On/Reset Options
Table 4-2: Host Bus Selection
CNF0
0
1
BS#
1
Big Endian
Generic #2, 16-bit
Host Bus Interface
1
X27A-G-013-02
S1D13705
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