S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 38

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 32
7.1.5 Generic #1 Interface Timing
S1D13705
X27A-A-001-09
Symbol
WE0#,WE1#
RD0#, RD1#
T
f
A[16:0]
D[15:0]
BCLK
D[15:0]
BCLK
BCLK
(write)
t10
t11
t1
t2
t3
t4
t5
t6
t7
t8
t9
WAIT#
(read)
CS#
Bus Clock frequency
Bus Clock period
A[16:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1#
low (read cycle)
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
A[16:0], CS# invalid
WE0#, WE1# high to D[15:0] invalid (write cycle)
D[15:0] valid to WAIT# high (read cycle)
WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to
WAIT# driven low
BCLK to WAIT# high
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to
WAIT# high impedance
WAIT# high to WE0#, WE1#, RD0#, RD1# high
WE0#, WE1# low to D[15:0] valid (write cycle)
RD0#, RD1# low to D[15:0] driven (read cycle)
RD0#, RD1# high to D[15:0] high impedance (read cycle)
T
BCLK
Hi-Z
Hi-Z
Hi-Z
Note
t1
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 83
t8
t3
t4
Parameter
Table 7-5: Generic #1 Timing
Figure 7-5: Generic #1 Timing
VALID
t9
VALID
t6
1T
1/f
Min
BCLK
BCLK
0
0
0
0
t11
Epson Research and Development
VALID
Hardware Functional Specification
T
Vancouver Design Center
Max
BCLK
50
17
10
16
16
16
Issue Date: 01/05/22
t2
t5
t10
t7
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hi-Z
Hi-Z