S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 55

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Epson Research and Development
Vancouver Design Center
7.3.9 Dual Color 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Hardware Functional Specification
Issue Date: 01/05/22
DRDY (MOD)
DRDY (MOD)
FPDAT[7:0]
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
FPFRAME
FPSHIFT
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
FPLINE
FPLINE
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
241-G1
241-R 1
241-B1
241-R 2
1-R2
1-R 1
1-G1
1-B1
Figure 7-22: Dual Color 8-Bit Panel Timing
241-G2
241-R3
241-G3
LINE 1/241
24 1-B2
1-G3
1-G2
1-B2
1-R 3
241-R 4
241-B3
241-G4
241-B4
1-B3
1-R4
1-G4
1-B4
LINE 2/242
241-R5
241-G 5
241-B5
241-R 6
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
1-G5
1-R 5
1-B5
1-R6
241-G6
241-B6
241-G7
241-R7
1-G6
1-R7
1-G7
1-B6
241-R8
241-B7
241-G8
241-B8
1-B7
1-R8
1-G8
1-B8
VDP
HDP
LINE 239/479 LINE 240/480
1-R640
1-G640
1-B640
1-B639
B639
R640
G640
B640
2 41-
241-
241-
241-
VNDP
HNDP
LINE 1/241
X27A-A-001-09
S1D13705
Page 49

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