S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 35
S1D13705
Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13705.pdf
(480 pages)
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Quantity
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Manufacturer:
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Quantity:
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Part Number:
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Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/05/22
Symbol
T
f
CKIO
t10
t11
t12
t13
t14
t15
t16
t17
CKIO
t2
t3
t4
t5
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
Bus Clock pulse width low
Bus Clock pulse width high
A[16:0], RD/WR# setup to CKIO
A[16:0], RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to DB[15:0] driven
CKIO to WEn#, RD# high
Rising edge CSn# to WAIT# high impedance
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
DB[15:0] setup to 2
DB[15:0] hold from rising edge of WEn# (write cycle)
DB[15:0] valid to WAIT# rising edge setup time (read cycle)
Rising edge RD# to DB[15:0] high impedance (read cycle)
Note
CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 83
nd
a
CKIO after BS# (write cycle)
One Software WAIT State Required
Parameter
Table 7-2: SH-3 Bus Timing
1.5T
1/f
Min
CKIO
8
8
0
0
5
5
0
0
0
0
CKIO
Max
50
25
10
15
20
10
a
Units
X27A-A-001-09
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S1D13705
Page 29
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