S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 406

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 20
4.5 Test Software
BR4
OR4
MemStart
RevCodeReg
Start
Loop
end
S1D13705
X27A-G-010-02
equ
equ
equ
equ
mfspr
andis.
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stw
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ori
stw
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lbz
b
The test software to exercise this interface is very simple. It configures chip select 4 on the
MPC821 to map the S1D13705 to an unused 128k byte block of address space and loads
the appropriate values into the option register for CS4. At that point the software runs in a
tight loop reading the 13705 Revision Code Register REG[00h], which allows monitoring
of the bus timing on a logic analyzer.
The source code for this test routine is as follows:
$120
$124
$40
1FFE0
r1,IMMR
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
r2,r2,$0708
r2,OR4(r1)
r1,r0,0
r1,r1,MemStart
r0,RevCodeReg(r1) ; read revision code into r1
Loop
; CS4 base register
; CS4 option register
; upper word of S1D13705 start address
; address of Revision Code Register
; get base address of internal registers
; clear lower 16 bits to 0
; clear r2
; write base address
; port size 16 bits; select GPCM; enable
; write value to base register
; clear r2
; address mask – use upper 10 bits
; normal CS negation; delay CS ½ clock;
; inhibit burst
; write to option register
; clear r1
; point r1 to start of S1D13705 mem space
; branch forever
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/13

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