S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 54

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 48
1. Ts
2. t1
3. t3
5. t6
6. t7
S1D13705
X27A-A-001-09
Symbol
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
Data Timing
Sync Timing
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse falling edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:0] setup to Shift Pulse falling edge
FPDAT[7:0] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
= pixel clock period
= t3
= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 20]Ts
= [((REG[08h] bits 4-0) x 2)x 8 + 29]Ts
min
- 9Ts
DRDY (MOD)
Frame Pulse
FPDAT[7:0]
Shift Pulse
Line Pulse
Line Pulse
Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing
Table 7-15: Dual Monochrome 8-Bit Panel A.C. Timing
Parameter
t6
t5
t7
t1
t14
t4
t8
t2
t12
t14 + 2
note 2
note 3
note 5
note 6
Min
39
9
9
1
8
4
4
4
4
1
t13
t3
t11
Epson Research and Development
Typ
Hardware Functional Specification
t9
2
t10
Vancouver Design Center
Max
Issue Date: 01/05/22
(note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts