S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 118

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 26
5.1.1 Registers
5.1.2 Examples
S1D13705
X27A-G-002-02
REG[11h] Memory Address Offset Register
Memory
Address
Offset
Bit 7
Memory
Address
Offset
Bit 6
Note
Memory Address Offset Register
REG[11h] forms an 8-bit value called the Memory Address Offset. This offset is the
number of additional words on each line of the display. If the offset is set to zero there is
no virtual width.
Example 1: In this example we go through the calculations to display a 640x480 im-
Step 1: Calculate the number of pixels per word for this color depth.
At 2 bpp each byte is comprised of 4 pixels, therefore each word contains 8 pixels.
pixels_per_word = 16 / bpp = 16 / 2 = 8
Step 2: Calculate the Memory Address Offset register value
We require a total of 640 pixels. The horizontal display register will account for 320 pixels,
this leaves 320 pixels for the Memory Address Offset register to account for.
offset = pixels / pixels_per_word = 320 / 8 = 40 = 28h
The Memory Address Offset register, REG[11h], will have to be set to 28h to satisfy the
above condition.
This value does not represent the number of words to be shown on the display. The dis-
play width is set in the Horizontal Display Width register.
Memory
Address
Offset
Bit 5
age on a 320x240 panel at 2 bpp.
Address
Memory
Offset
Bit 4
Memory
Address
Offset
Bit 3
Memory
Address
Offset
Bit 2
Epson Research and Development
Programming Notes and Examples
Memory
Address
Offset
Bit 1
Vancouver Design Center
Issue Date: 01/02/13
Address
Memory
Offset
Bit 0