S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 333

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Using The Generic #1 Host Bus Interface
Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
Issue Date: 01/02/13
Figure 2-2: Typical Implementation of MC68328 to S1D13705 Interface - Generic #1
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
If UDS and/or LDS are required for their alternate IO functions, then the MC68328 to
S1D13705 interface may be implemented using the S1D13705 Generic #1 host bus
interface. Note that in either case, the DTACK signal must be made available for the
S1D13705, since it inserts a variable number of wait states depending upon CPU/LCD
synchronization and the LCD panel display mode. WAIT# must be inverted (using an
inverter enabled by CS#) to make it an active high signal and thus compatible with the
MC68328 architecture. A single resistor is used to pull up the WAIT# (DTACK) signal
when terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to S1D13705
using the Generic #1 host bus interface. For further information on the Generic #1 host bus
interface and AC Timing, refer to the S1D13705 Hardware Functional Specification,
document number X27A-A-001-xx.
MC68328
DTACK
UWE
CLK0
D[15:0]
A[16:0]
LWE
CSB3
OE
Vcc
1K
System RESET
WE0#
AB[16:0]
DB[15:0]
WAIT#
RD/WR#
RD#
BUSCLK
WE1#
RESET#
CS#
BS#
S1D13705
X27A-G-007-04
S1D13705
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