S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 127

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
6 LCD Power Sequencing and Power Save Modes
6.1 LCD Power Sequencing
6.2 Registers
Programming Notes and Examples
Issue Date: 01/02/13
REG[03h] Mode Register 2
Correct power sequencing is required to prevent long term damage to LCD panels and to
avoid unsightly" lines" during power-up and power-down. Power Sequencing allows the
LCD power supply to discharge prior to shutting down the LCD logic signals.
Proper LCD power sequencing dictates there must be a time delay between the LCD power
being disabled and the LCD signals being shut down. During power-up the LCD signals
must be active prior to or when power is applied to the LCD. The time intervals vary
depending on the power supply design.
The S1D13705 performs automatic power sequencing in response to both software power
save (REG[03h]) or in response to a hardware power save. One frame after a power save
mode is set, the S1D13705 disables LCD power, and the LCD logic signals continue for
one hundred and twenty seven frames allowing the LCD power supply to completely
discharge. For most applications the internal power sequencing is the appropriate choice.
There may be situations where the internal time delay is insufficient to discharge the LCD
power supply before the LCD signals are shut down, or the delay is too long and the
designer wishes to shorten it. This section details the sequences to manually power-up and
power-down the LCD interface.
The LCD Power (LCDPWR) Override bit forces LCD power inactive one frame after being
toggled. As long as this bit is "1" LCD power will be disabled.
The Hardware Power Save Enable bit must be set in order to activate hardware power save
through GPIO0.
The Software Power Save bits set and reset the software power save mode. These bits are
set to "11" for normal opertion and set to "00" for power save mode.
LCD logic signals to the display panel are active for 128 frames after setting either
hardware or software power save modes. Power sequencing overide is performed by setting
the LCDPWR Override bit some time before setting a power save mode for power off
sequences. During power on sequences the power save mode is reset some time before the
LCDPWR Override is reset resulting in the LCD logic signals being active before power is
applied to the panel.
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save
bit 1
Software
Power Save
bit 0
X27A-G-002-02
S1D13705
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