S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 89

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
13.5 Turning Off BCLK Between Accesses
Hardware Functional Specification
Issue Date: 01/05/22
Hardware Power Save
Software Power Save
(except LCDPWR)
Panel Interface
REG[03h] bits [1:0]
Output Signals
or
LCDPWR
RESET#
After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are
held “low”. Software initializes the chip (i.e. programs all registers except the Look-Up
Table registers) and then programs REG[03h] bits [1:0] to 11b. This starts the power-up
sequence as shown. The power-up/power-down sequence delay is 127 frames. The Look-
Up Table registers may be programmed any time after REG[03h] bits[1:0] = 11b.
The power-up/power-down sequence also occurs when exiting/entering Software Power
Save Mode.
BCLK may be turned off (held low) between accesses if the following rules are observed:
1. BCLK must be turned off/on in a glitch free manner
2. BCLK must continue for a period equal to [8T
3. BCLK must be present for at least one T
access (RDY# asserted or WAIT# deasserted).
00
Figure 13-1: Panel On/Off Sequence
power-up
0 frame
11
127 frames
power-down
BCLK
Power Save Mode
BCLK
before the start of an access.
00
+ 12T
MCLK
power-up
0 frame
] after the end of the
11
X27A-A-001-09
S1D13705
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