S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 70

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 64
bits 7-0
S1D13705
X27A-A-001-09
REG[15h] Look-Up Table Address Register
Address = 1FFF5h
LUT Address
Where:
(REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address
BPP is Bits-per-Pixel as set by REG[02h] bits 7:6
REG[11h] is the Address Pitch Adjustment in Words
(REG[0Fh], REG[0Eh]) is the Screen 2 Start Word Address
(REG[13h], REG[12h]) is the Screen 1 Vertical Size
(REG[06h], REG[05h]) is the Vertical Panel Size
Bit 7
Image 2
Image 1
LUT Address
Bit 6
(REG[0Dh], REG[0Ch]) Words
Consider an example where REG[13h], REG[12] = 0CEh for a 320x240 display system.
The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word
Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.
LUT Address Bits [7:0]
These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13705 has three
256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 11,
“Look-Up Table Architecture” on page 70 for details.
This register selects which LUT entry is read/write accessible through the LUT Data Reg-
ister (REG[17h]). Writing the LUT Address Register automatically sets the pointer to the
Red LUT. Accesses to the LUT Data Register automatically increment the pointer.
For example, writing a value 03h into the LUT Address Register sets the pointer to R[3].
A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto
G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4],
G[4], B[4], R[5], etc.
(REG[0Fh], REG[0Eh]) Words
LUT Address
Figure 8-1: Screen-Register Relationship, Split Screen
Line 0 Last Pixel Address + REG[11h] Words
Bit 5
Line=(REG[13h], REG[12h])
8(REG[04h]+1) Pixels
LUT Address
Line 0
Line 1
Bit 4
Virtual Image
LUT Address
Bit 3
Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +
LUT Address
REG[11h] Words
Bit 2
Epson Research and Development
Hardware Functional Specification
LUT Address
(8(REG[04h]+1)
Words
((REG[06h], REG[05])+1) Lines
Bit 1
Vancouver Design Center
Issue Date: 01/05/22
Read/Write
LUT Address
BPP/16))
Bit 0