S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 53

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Epson Research and Development
Vancouver Design Center
7.3.8 Dual Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Hardware Functional Specification
Issue Date: 01/05/22
* Diagram drawn with 2 FPLINE vertical blank period
DRDY (MOD)
DRDY (MOD)
Example timing for a 640x480 panel
FPDAT[7:0]
FPFRAME
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
FPSHIFT
FPLINE
FPLINE
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Figure 7-20: Dual Monochrome 8-Bit Panel Timing
241-1
241-2
241-3
241-4
1-1
1-2
1-3
1-4
LINE 1/241
241-5
241-6
241-7
241-8
1-5
1-6
1-7
1-8
LINE 2/242
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
LINE 3/243
LINE 4/244
VDP
HDP
LINE 239/479 LINE 240/480
VNDP
241-637
241-638
241-639
241-640
1-637
1-638
1-639
1-640
HNDP
LINE 1/241
LINE 2/242
X27A-A-001-09
S1D13705
Page 47

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