S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 25

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/05/22
Pin Names
RD/WR#
WE0#
WE1#
BCLK
CS#
BS#
Type
I
I
I
I
I
I
Pin #
77
78
74
71
75
79
Cell
CS
CS
CS
CS
C
C
RESET#
State
Input
Input
Input
Input
Input
Input
This pin has multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
This pin has multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
This pin inputs the chip select signal.
This pin inputs the system bus clock.
This pin has multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
This pin has multiple functions.
See Table 5-2: “Host Bus Interface Pin Mapping,” on page 22 for
summary.
• For SH-3/SH-4 mode, this pin inputs the write enable signal
• For MC68K #1, this pin must be tied to IO V
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic #1, this pin inputs the write enable signal for the
• For Generic #2, this pin inputs the write enable signal (WE#)
• For SH-3/SH-4 mode, this pin inputs the write enable signal
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For Generic #1, this pin inputs the write enable signal for the
• For Generic #2, this pin inputs the byte enable signal for the
• For SH-3/SH-4 mode, this pin inputs the bus start signal
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For Generic #1, this pin must be tied to V
• For Generic #2, this pin must be tied to IO V
• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal.
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For Generic #1, this pin inputs the read command for the
• For Generic #2, this pin must be tied to IO V
for the lower data byte (WE0#).
lower data byte (WE0#).
for the upper data byte (WE1#).
upper data byte (WE1#).
high data byte (BHE#).
(BS#).
The S1D13705 needs this signal for early decode of the bus
cycle.
upper data byte (RD1#).
Description
SS
.
DD
DD
DD
.
.
X27A-A-001-09
S1D13705
Page 19