S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 361

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Epson Research and Development
Vancouver Design Center
2.1.2 LCD Memory Access Cycles
Interfacing to the NEC VR4102/VR4111 Microprocessor
Issue Date: 01/02/13
LCDRDY
ADD[25:0]
D[15:0]
D[15:0]
LCDCS#
WR#,RD#
(write)
TCLK
(read)
SHB#
Once an address in the LCD block of memory is placed on the external address bus,
ADD[25:0], the LCD chip select, LCDCS#, is driven low. The read or write enable signals,
RD# and WR#, are driven low for the appropriate cycle. LCDRDY is driven low by the
S1D13705 to insert wait states into the cycle. The high byte enable is driven low for 16-bit
transfers and high for 8-bit transfers.
Figure 2-1: “NEC VR4102/VR4111 Read/Write Cycles,” on page 9 shows the read and
write cycles to the LCD Controller Interface.
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles
Hi-Z
VALID
VALID
VALID
X27A-G-008-02
S1D13705
Hi-Z
Page 9

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