S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 440
S1D13705
Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13705.pdf
(480 pages)
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Page 12
4 Direct Connection to the Philips PR31500/PR31700
4.1 General Description
S1D13705
X27A-G-012-02
/CARDIOREAD
ENDIAN
PR31500/PR31700
/CARD1WAIT
/CARDIOWR
/CARD1CSH
/CARD1CSL
DCLKOUT
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
D[31:24]
D[23:16]
A[12:0]
ALE
Note
In this example implementation the S1D13705 occupies the PR31500/PR31700 PC Card
slot #1.
The S1D13705 is easily interfaced to the PR31500/PR31700 with minimal additional logic.
The address bus of the PR31500/PR31700 PC Card interface is multiplexed and must be
demultiplexed using an advanced CMOS latch (e.g., 74AHC373). The direct connection
approach makes use of the S1D13705 in its “Generic #2” interface configuration.
The following diagram demonstrates a typical implementation of the interface.
Figure 4-1: S1D13705 to PR31500/PR31700 Direct Connection
See Section 3.1 on page 9 and Section 3.3 on page 11 for Generic #2 pin descriptions.
Latch
V
DD
Clock divider
pull-up
...or...
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Oscillator
System RESET
+3.3V
+3.3V
+3.3V
See text
Epson Research and Development
BS#
RD/WR#
IO V
RD#
WE0#
WE1#
CLKI
BCLK
AB[16:13]
AB[12:0]
DB[7:0]
WAIT#
RESET#
CS#
DB[15:8]
S1D13705
DD
, CORE V
Vancouver Design Center
Issue Date: 01/02/13
DD
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