S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 73

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
bit 2
bits 1-0
bits 7-0
REG[1Eh] and REG[1Fh]
Hardware Functional Specification
Issue Date: 01/05/22
REG[1Ch] Line Byte Count Register for SwivelView Mode
Address = 1FFFCh
Count bit 7
Line Byte
Count bit 6
Line Byte
Mode Enable
(REG[1Bh] bit 7)
SwivelView
0
1
1
1
1
1
1
1
1
REG[1Eh] and REG[1Fh] are reserved for factory S1D13705 testing and should not be
written. Any value written to these registers may result in damage to the S1D13705 and/or
any panel connected to the S1D13705.
reserved
reserved bits must be set to 0.
SwivelView Mode Pixel Clock Select Bits [1:0]
These two bits select the Pixel Clock (PCLK) source in SwivelView Mode - these bits
have no effect in Landscape Mode. The following table shows the selection of PCLK and
MCLK in SwivelView Mode - see Section 12, “SwivelView™” on page 76 for details.
Line Byte Count Bits [7:0]
This register is the byte count from the beginning of one line to the beginning of the next
consecutive line (commonly called “stride” by programmers). This register may be used to
create a virtual image in SwivelView mode.
When this register = 00 the “stride” = 256 bytes. This value is used for 240x320 8 bpp
default SwivelView mode
When the Line Byte Count Register = n, where 1 n
Count bit 5
Line Byte
Table 8-8: Selection of PCLK and MCLK in SwivelView Mode
(REG[1Bh] bit 6)
Mode Select
SwivelView
X
0
0
0
0
1
1
1
1
Count bit 4
Line Byte
Pixel Clock (PCLK) Select
Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)
Bit 1
(REG[1Bh] bits [1:0]
X
0
0
1
1
0
0
1
1
Count bit 3
Line Byte
Bit 0
X
0
1
0
1
0
1
0
1
Count bit 2
Line Byte
FFh, the “stride” = n bytes.
PCLK =
CLK/2
CLK/4
CLK/8
CLK/2
CLK/2
CLK/4
CLK/8
CLK
CLK
Count bit
Line Byte
See Reg[02h] bit 5
1
MCLK =
Read/Write
CLK/2
CLK/4
CLK/8
CLK/2
CLK/4
X27A-A-001-09
Count bit
CLK
CLK
CLK
Line Byte
S1D13705
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