S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 345

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
4.3.3 MC68K #1 Interface Mode
Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
Issue Date: 01/02/13
The MC68K #1 Interface Mode can be used to interface to the MC68VZ328 micropro-
cessor if the previously mentioned, multiplexed, bus signals will not be used for other
purposes.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
• The address inputs AB1 through AB16, and the data bus DB0 through DB15, connect
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
• A0 and WE1# are the enables for the low-order and high-order bytes, respectively, to be
• RD/WR# is the read/write signal that is driven low when the CPU writes to the
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates
• The Bus Status (BS#) signal indicates that the address on the address bus is valid.
• The WE0# and RD# signals is not used in the bus interface for MC68K #1 and must be
S1D13705. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
register and memory address space.
driven low when the host CPU is reading or writing data to the S1D13705.
S1D13705 and is driven high when the CPU is doing a read from the S1D13705.
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the S1D13705 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13705 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete.
tied high (tied to IO V
DD
).
X27A-G-007-04
S1D13705
Page 25