S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 396

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 10
2.2.2 Burst Cycles
S1D13705
X27A-G-010-02
TSIZ[0:1], AT[0:3]
Note
Figure 2-2: “Power PC Memory Write Cycle” illustrates a typical memory write cycle on
the Power PC system bus.
If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is
aborted. For example, a peripheral device may assert TEA if a parity error is detected, or
the MPC821 bus controller may assert TEA if no peripheral device responds at the
addressed memory location within a bus time-out period.
For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines
A30 and A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and
address line A30 is ignored. For 8-bit transfers, data lines D0 through D7 are used and all
address lines (A[0:31]) are used.
Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip
DMA operations. They are very similar to normal bus cycles with the following exceptions:
• Always 32-bit.
• Always attempt to transfer four 32-bit words sequentially.
• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).
• Do not increment address bits A28 and A29 between successive transfers; the addressed
This assumes that the Power PC core is operating in big endian mode (typically the case
for embedded systems).
device must increment these address bits internally.
SYSCLK
RD/WR
D[0:31]
A[0:31]
Transfer Start
TS
TA
Figure 2-2: Power PC Memory Write Cycle
Valid
Wait States
Complete
Transfer
Interfacing to the Motorola MPC821 Microprocessor
Next Transfer
Epson Research and Development
Starts
Vancouver Design Center
Issue Date: 01/02/13