S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 177

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 1
S1D13705 Register Summary
S1D13705 Register Summary
Disp Status
REG[00h] R
REG[01h] M
REG[02h] M
REG[03h] M
REG[04h] H
REG[05h] V
REG[06h] V
REG[07h] FPL
REG[08h] H
REG[09h] FPF
REG[0Ah] V
Vert Non-
REG[0Bh] MOD R
REG[0Ch] S
REG[0Dh] S
REG[0Eh] S
REG[0Fh] S
REG[10h] S
TFT/STN
Bit 15
Bit 15
Bit 5
Bit 1
Bit 7
Bit 7
Bit 7
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Bit-Per-Pixel
EVISION
ORIZONTAL
ERTICAL
ERTICAL
ORIZONTAL
CREEN
CREEN
CREEN
ODE
Dual/Single Color/Mono
ODE
ODE
ERTICAL
CREEN
CREEN
INE
RAME
Bit 14
Bit 14
Bit 4
Bit 0
Bit 6
Bit 6
Bit 6
Bit 6
n/a
n/a
n/a
n/a
n/a
n/a
n/a
R
R
R
3
Screen 1 Start Word Address = (REG[0Ch], REG[0Dh], REG[10] bit 1)
S
ATE
Screen 2 Start Word Address = (REG[0E], REG[0Fh], REG[10] bit 4)
EGISTER
EGISTER
EGISTER
2 S
2 S
S
1 S
1 S
TART
C
P
P
TART
S
N
ODE
ANEL
ANEL
TART
ON
R
TART
TART
TART
TART
P
N
EGISTER
ANEL
ON
P
-D
Performance
A
R
Product Code = 001001
0
1
2
OSITION
S
S
ISPLAY
DDRESS
EGISTER
-D
P
W
W
W
W
Vertical Panel Size = (REG[05h], REG[06h]) + 1
High
IZE
IZE
OSITION
Bit 13
Bit 13
Bit 3
IO address = 1FFE1h, RW
IO address = 1FFE2h, RW
IO address = 1FFE3h, RW
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
ISPLAY
ORD
n/a
S
n/a
n/a
n/a
ORD
ORD
ORD
IZE
R
R
IO address = 1FFEBh, RW
5
EGISTER
EGISTER
P
A
A
A
A
R
IO address = 1FFE7h, RW
O
ERIOD
1
DDRESS
DDRESS
DDRESS
DDRESS
EGISTER
3
P
VERFLOW
IO address = 1FFE9h, RW
Screen 1 Start Word Address
Screen 2 Start Word Address
ERIOD
IO address = 1FFE0h
Div (CLKI/2)
Input Clock
Start Add
Screen 2
Horizontal Panel Size = 8(REG + 1)
Polarity
FPLine
(LSB)
(MSB)
R
Bit 12
Bit 12
Bit 16
Bit 2
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
n/a
n/a
EGISTER
R
R
R
R
IO address = 1FFE8h, RW
IO address = 1FFE4h, RW
EGISTER
EGISTER
EGISTER
EGISTER
R
EGISTER
IO address = 1FFE5h, RW
IO address = 1FFE6h, RW
Horizontal Non-Display Period = 8(REG + 4)
Vertical Non-Display Period
FPLine Start Position = 8(REG[07h] + 2)
IO address = 1FFEAh, RW
LCDPWR
FPFrame Start Position
(MSB)
FPFrame
(LSB)
(MSB)
(LSB)
Override
Polarity
Display
Blank
Bit 11
Bit 11
)
Bit 1
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
n/a
IO address = 1FFF0h, RW
MOD Rate
2
IO address = 1FFECh, RW
IO address = 1FFEEh, RW
, RO
IO address = 1FFEDh, RW
IO address = 1FFEFh, RW
PS Enable
Hardware
FPSHIFT
Repeat
Frame
Mask
Bit 10
Bit 10
Bit 0
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
n/a
Hw Video
Enable
Revision Code = 00
Invert
Vertical Panel Size
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
Bit 1
Bit 9
Sw Power Save
Data Width
Video Invert
Software
Screen 1
Start Add
Bit 16
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
4
6
Notes
1 These bits are used to identify the S1D13705 at power on / reset.
2 IO addresses are relative to the beginning of display memory.
3 Gray Shade/Color Mode Selection
SwivelView
REG[11h] M
REG[12h] S
REG[13h] S
REG[15h] L
REG[17h] L
REG[18h] GPIO C
REG[19h] GPIO S
REG[1Ah] S
REG[1Bh] S
Mode En.
REG[1Ch] L
Color/Mono
REG[01] bit 5
Bit 7
Bit 7
Bit 7
Bit 3
Bit 7
Bit 7
n/a
n/a
n/a
1
0
CREEN
CREEN
OOK
OOK
EMORY
CRATCH
WIVEL
INE
SwivelView
Mode Sel.
Look-Up Table Data
Bit 6
Bit 6
-U
Bit 6
-U
Bit 2
Bit 6
B
Bit 6
n/a
n/a
n/a
YTE
V
P
P
ONFIGURATION
TATUS
1 V
1 V
Bit-Per-Pixel Bit 1
A
IEW
T
T
P
DDRESS
REG[02] bit 7
ABLE
ABLE
C
AD
ERTICAL
ERTICAL
M
OUNT
/ C
R
ODE
A
D
EGISTER
0
1
0
1
ONTROL
Screen 1 Vertical Size = (REG[12h], REG[13h])
DDRESS
ATA
R
O
Bit 5
Bit 5
Bit 5
Bit 1
Bit 5
Bit 5
R
n/a
n/a
n/a
n/a
S
S
EGISTER
FFSET
EGISTER
IZE
IZE
C
R
EGISTER
ONTROL
R
R
R
IO address = 1FFFAh, RW
R
EGISTER
EGISTER
R
EGISTER
EGISTER
EGISTER
IO address = 1FFFCh, RW
GPIO4 Pin
GPIO4 Pin
Memory Address Offset
Look-Up Table Address
IO Config
IO Status
IO address = 1FFFBh, RW
Scratch Pad Register
Bit-Per-Pixel Bit 0
R
Bit 4
Bit 4
Bit 4
Bit 0
Bit 4
Bit 4
n/a
IO address = 1FFF7h, RW
n/a
EGISTER
Line Byte Count
REG[02] bit 6
(LSB)
(MSB)
IO address = 1FFF9h, RW
IO address = 1FFF5h, RW
IO address = 1FFF1h, RW
0
1
0
1
0
1
0
1
IO address = 1FFF3h, RW
IO address = 1FFF8h, RW
IO address = 1FFF2h, RW
GPIO3 Pin
GPIO3 Pin
IO Config
IO Status
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
n/a
n/a
n/a
16 Gray Shade
2 Gray Shade
4 Gray Shade
GPIO2 Pin
GPIO2 Pin
IO Config
IO Status
reserved
256 Colors
16 Colors
2 Colors
4 Colors
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
n/a
n/a
Display Mode
n/a
reserved
GPIO1 Pin
GPIO1 Pin
SwivelView PCLK Select
IO Config
IO Status
Screen 1 Vertical Size
Bit 1
Bit 1
Bit 9
Bit 1
Bit 1
Bit 1
Bit 1
1 Bit-Per-Pixel
2 Bit-Per-Pixel
4 Bit-Per-Pixel
8 Bit-Per-Pixel
1 Bit-Per-Pixel
2 Bit-Per-Pixel
4 Bit-Per-Pixel
n/a
GPIO0 Pin
GPIO0 Pin
IO Config
IO Status
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
4 Panel Data Format
5 High Performance Selection
6 Power Save Mode Selection
TFT/STN
REG[01]
bit 7
High Performance
Power Save Bit 1
0
1
0
1
0
0
1
1
Color/
Mono
REG[01]
bit 5
0
1
REG[02] bit 7
Bit-Per-Pixel
don’t care
Dual/
Single
REG[01]
bit 6
Bit 1
0
1
X
0
1
0
1
Power Save Bit 0
0
1
0
1
Data
Width
Bit 1
REG[01]
bit 1
REG[02] bit 6
Bit-Per-Pixel
0
1
0
1
0
1
0
1
Bit 0
0
1
0
1
X
Data
Width
Bit 0
REG[01]
bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MClk = PClk/8
MClk = PClk/4
MClk = PClk/2
MClk = PClk
Power Save Mode 1
Normal Operation
X27A-R-001-03
X27A-R-001-03
Color Single 8-bit LCD Format 1
Color Single 8-bit LCD Format 2
reserved
reserved
Display Modes
Mode
MClk = PClk
Mono Single 4-bit LCD
Mono Single 8-bit LCD
Color Single 4-bit LCD
Mono Dual 8-bit LCD
Color Dual 8-bit LCD
12 bit TFT Panel
9 bit TFT Panel
01/02/13
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Function
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
8 bit-per-pixel