S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 364

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S1D13705

Manufacturer Part Number
S1D13705
Description
S1d13705 Embedded Memory Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 12
4 VR4102/VR4111 to S1D13705 Interface
4.1 Hardware Description
S1D13705
X27A-G-008-02
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
NEC VR4102/VR4111
DATA[15:0]
ADD[16:0]
Figure 4-1: Typical Implementation of VR4102/VR4111 to S1D13705 Interface
LCDRDY
BUSCLK
LCDCS#
SHB#
WR#
RD#
The NEC VR4102/VR4111 Microprocessor is specifically designed to support an external
LCD controller by providing the internal address decoding and control signals necessary.
By using the Generic # 2 interface, no glue logic is required to interface the S1D13705 and
the NEC VR4102/VR4111. A pull-up resistor is attached to WAIT# to speed up its rise time
when terminating a cycle.
The following diagram shows a typical implementation of the VR4102/VR4111 to
S1D13705 interface.
Pull-up
Interfacing to the NEC VR4102/VR4111 Microprocessor
System RESET
Vcc
Vcc
Epson Research and Development
RD#
WE1#
RD/WR#
CS#
WAIT#
RESET#
AB[16:0]
DB[15:0]
BUSCLK
BS#
WE0#
S1D13705
Vancouver Design Center
Issue Date: 01/02/13

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