S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 44

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 38
1. Ts
2. t1
3. t3
4. t6
5. t7
S1D13705
X27A-A-001-09
Symbol
t10
t11
t12
t13
t14
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
t1
t2
t3
t4
t5
t6
t7
t8
t9
min
min
min
min
Data Timing
Sync Timing
= pixel clock period
= t3
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 2]Ts
= [(REG[08h] bits 4-0) x 8 + 11]Ts
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:4] setup to Shift Pulse falling edge
FPDAT[7:4] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
min
- 9Ts
DRDY (MOD)
Frame Pulse
FPDAT[7:4]
Shift Pulse
Line Pulse
Line Pulse
Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing
Table 7-10: Single Monochrome 4-Bit Panel A.C. Timing
Parameter
t5
t6
t7
t1
t14
t4
t8
t14 + 2
t12
note 2
note 3
note 4
note 5
Min
23
9
9
1
4
2
2
2
2
t2
1
t3
t13
Epson Research and Development
t11
Hardware Functional Specification
Typ
t9
2
t10
Vancouver Design Center
Max
Issue Date: 01/05/22
(note 1)
Units
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts