S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 457

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

EPSON Research and Development
Vancouver Design Center
2.2 Generic #2 Interface Mode
S5U13704/5 - TMPR3912/22U CPU Module
Issue Date: 01/03/07
Generic #2 interface mode is a general and non-processor-specific interface mode on the
S1D13704/5. The Generic # 2 interface mode was chosen for this interface due to its
compatibility with the PC Card interface.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
• WE1# is the high byte enable for both read and write cycles and WE0# is the enable
• RD# is the read enable for the S1D13704/5, to be driven low when the host CPU is
• WAIT# is a signal which is output from the S1D13704/5 to the host CPU that indicates
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
S1D13704/5. BUSCLK is separate from the input clock (CLKI) and is typically driven
by the host CPU system clock.
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
memory address space.
signal for a write access. These must be generated by external decode hardware based
upon the control outputs from the host CPU.
reading data from the S1D13704/5. RD# must be generated by external decode hard-
ware based upon the control outputs from the host CPU.
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the S1D13704/5 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 13704/5 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
face for Generic #2 mode. However, BS# is used to configure the S1D13704/5 for
Generic #2 mode and must be tied high (connected to IOVDD = 3.3V). RD/WR# must
also be tied high.
X00A-G-004-02
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