S1D13705 Epson Electronics America, Inc., S1D13705 Datasheet - Page 62

• Manufacturer Part Number: S1D13705
• Description: S1d13705 Embedded Memory Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 56
bits 7-6
bit 5
S1D13705
X27A-A-001-09
REG[02h] Mode Register 1
Address = 1FFE2h
Bit-Per-Pixel
Bit 1
Bit-Per-Pixel
Bit 0
Bit-Per-Pixel Bits [1:0]
These bits select the color or gray-scale depth (Display Mode).
High Performance (Landscape Modes Only)
When this bit = 0, the internal Memory Clock (MCLK) is a divided-down version of the
Pixel Clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the
table below.
When this bit = 1, MCLK is fixed to the same frequency as PCLK for all bit-per-pixel
modes. This provides a faster screen update performance in 1/2/4 bit-per-pixel modes, but
also increases power consumption. This bit can be set to 1 just before a major screen
update, then set back to 0 to save power after the update. This bit has no effect in Swivel-
View mode. Refer to REG[1Bh] SwivelView Mode Register on page 66 for SwivelView
mode clock selection.
High Performance
Color/Mono
REG[01h] bit 5
Performance
0
1
High
0
1
Bit-Per-Pixel Bit 1
Input Clock
REG[02h] bit 7
(CLKI/2)
Table 8-3: High Performance Selection
divide
Table 8-2: Gray Scale/Color Mode Selection
BPP Bit 1
0
1
0
1
X
0
1
Display Blank
Bit-Per-Pixel Bit 0
BPP Bit 0
REG[02h] bit 6
0
1
0
1
X
0
1
0
1
0
1
0
1
Repeat
Frame
MClk = PClk/8
MClk = PClk/4
MClk = PClk/2
MClk = PClk
16 Gray scale
Epson Research and Development
2 Gray scale
4 Gray scale
Display Modes
256 Colors
16 Colors
MClk = PClk
2 Colors
4 Colors
Hardware Functional Specification
Video Invert
Hardware
Enable
Display Mode
Vancouver Design Center
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
8 bit-per-pixel
reserved
Issue Date: 01/05/22
Read/Write.
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
1 bit-per-pixel
2 bit-per-pixel
4 bit-per-pixel
8 bit-per-pixel
Video Invert
Software